Integrated circuits comprise a semiconductor substrate and semiconductor devices, such as transistors, formed from doped regions within the substrate. An interconnect system comprising alternating conductive and dielectric layers overlying the substrate electrically connects the doped regions to form electrical circuits.
The conductive layers comprise conductive traces formed according to a metal deposition and subtractive etch process or conductive runners formed in trenches according to a damascene process. Substantially vertical conductive plugs or vias within the dielectric layers connect overlying and underlying conductive traces and runners, including connection to the doped regions in the substrate. The conductive vias and the conductive lines are formed by employing conventional fabrication techniques including metal deposition, photolithographic masking, patterning and subtractive etching.
After fabrication and metallization (fabrication of the interconnect system) the integrated circuit is enclosed in a package comprising a plurality of external conductive elements, such as leads, pins or balls, for connecting the packaged chip to electronic components in an electronic device, typically by conductively attaching the package's external conductive elements to conductive traces on a circuit board.
To connect the integrated circuit to the conductive elements of the package, an uppermost surface of the integrated circuit (referred to as the bond pad layer) comprises a plurality of conductive bond pads to which is attached a conductive element (e.g., a bond wire, solder bump or solder ball) that connects the bond pads to the package's external conductive elements. In an aluminum-based interconnect system, an uppermost deposited aluminum layer is masked, patterned and etched to form aluminum bond pads. Underlying conductive plugs connect the bonds pads to the electrical circuits of the integrated circuit.
FIG. 6 illustrates a integrated circuit dual-in-line package 100 comprising external package leads 102. An integrated circuit 104 is affixed to a die attach area 106. Bond pads 110 (in one embodiment formed from aluminum) on an upper surface 112 of the integrated circuit 104 are connected to the package leads 102 conventionally by gold (or gold alloy) bond wires 114. Generally, the bond pads 110 vary between about 40-80 microns and 50-150 microns in length and width, respectively. The process of electrically connecting the bond pads 110 to the package leads 102 is referred to as wire bonding.
In another known package structure, referred to as flip chip or bump bonding, the interconnecting bond wires are replaced with deposited solder bumps 120 formed on the bond pads 110 of an integrated circuit 121. See FIG. 7. Electrical connection of the flip chip assembly to a package 122 of FIG. 8 is accomplished by inverting the integrated circuit 121 and soldering the bumps 120 to receiving pads 124 on the package 122. The receiving pads 124 are in conductive communication with corresponding external package conductive elements through internal conductive structures not illustrated in FIG. 8. In the example of FIG. 8, the external package conductive elements comprise an array of balls 126, forming a ball grid array for electrically connecting the packaged integrated circuit 121 to an electronic device. Alternatively, the package comprises external pins such as the pins 102 of FIG. 6, or other techniques for connecting the integrated circuit 121 to the electronic device.
Integrated circuits formed with an aluminum interconnect system and aluminum bond pads 110 can be packaged using either the wire bond process illustrated in FIG. 6 or flip chip and bump bond process illustrated in FIGS. 7 and 8.
As integrated circuit devices and interconnect systems are reduced in size and made to carry higher frequency analog signals and higher data-rate digital signals, aluminum interconnect structures can impose unacceptable signal propagation delays within the chip. Also, as via openings continue to shrink it becomes increasingly difficult to deposit conductive material in the smaller openings to form the conductive plugs.
Given these known disadvantages of aluminum interconnect structures, copper (and its alloys) is becoming the interconnect material of choice. Copper is a better conductor than aluminum (with a resistivity of 1.7 to 2.0 micro-ohms-cm compared to 2.7 to 3.1 micro-ohms-cm for aluminum), is less susceptible to electromigration (a phenomenon whereby an aluminum interconnect line thins and can eventually separate due to the electric field and thermal gradients formed by current flow through the line) and can be deposited at lower temperatures (thereby avoiding deleterious effects on other elements of the integrated circuit) in smaller openings. The lower resistance of copper reduces signal propagation time within the interconnect structures.
A damascene process, a preferred technique for forming copper interconnect structures, integrally forms both the conductive vertical via portion and the conductive horizontal portion of each layer of the copper interconnect structure. The damascene process forms a vertical via opening followed by an overlying horizontal trench in a dielectric layer. A metal deposition step simultaneously fills both the via and the trench, forming a complete metal interconnect layer comprising a substantially vertical conductive via and a substantially horizontal conductive runner. A chemical/mechanical-polishing step planarizes the dielectric surface by removing copper deposits formed on the surface during copper deposition.
An example of a completed prior art damascene structure is illustrated in the cross-sectional view of FIG. 9, comprising a dielectric layer 138 deposited or formed on a lower level interconnect structure 139. An opening formed in the dielectric layer 138 is filled with a suitable conductive material 140, such as copper, to form a conductive trench 142 and a conductive via 144 in contact with the lower level interconnect structure 139. As is well known in the art, copper bond pads are formed in the topmost metalization layer of the integrated circuit when a damascene process is employed to form the conductive interconnect system.
Flip chip technology has become increasingly popular for devices having a large number of input/output terminals as the bumps can be formed over an entire face of the integrated circuit (referred to as area-array bump configurations) with a higher density than the bond pads 110 of FIG. 6. Area-array bump configurations offer significant advantages over wire bonding and are typically used where chip performance and/or form factor outweighs all other considerations. Peripheral-array bump configurations (in which one or two bump rows in a linear or staggered arrangement are disposed proximate a periphery of the integrated circuit) offer shorter interconnect distances and therefore shorter transmission delay times.
Although attempts have been made to apply wire bonds directly to copper bond pads, these techniques are not widely used in commercial fabrication processes because copper surfaces are easily oxidized and therefore are difficult to probe using conventional probe techniques. Flip-chip solder bump methods are more amenable for use with copper bond pads. Bumps can be formed on the copper and the bumps probed, but the in-process probing is still problematic. By contrast, the aluminum pad provides a well known electrical contact pad for in-process and wafer probing.
Flip chip technology can be costlier than conventional wire bonding technology as it requires additional processing steps. Two or more additional material layer depositions and at least an equal number of mask levels and etch steps are necessary to fabricate under-bump metallurgical layers that are required intermediate to the bonding pad and the solder bump.
Conventional flip chip fabrication processes also form dual passivation layer stacks (each layer may comprise sub-layers of different dielectric materials) on the upper surface of the integrated circuit. Each passivation layer is fabricated according to multi-layer dielectric deposition steps (which may be performed in one or more cluster tools), followed by patterning, lithographic, etch and post-etch steps. Semiconductor manufacturers seek to limit mask and etch steps to reduce processing costs.
A first passivation layer (often referred to as a wafer passivation layer) protects the upper or final copper metal interconnect layer and the copper pads disposed therein. A second passivation layer (often referred to as a final passivation layer) protects the aluminum pad formed over the copper pad.
FIG. 10 illustrates a final assembly of a solder bump or flip chip structure for a copper-based interconnect structure according to a conventional prior art process. A substrate 198 comprises multiple alternating layers of dielectric material and copper interconnects overlying a semiconductor material in which doped regions have been formed. Copper bond pads 200 are formed within a trench or opening of the substrate 198 according to a damascene process for connecting the interconnect structures within the substrate 198 (and thus the electrical circuits within the substrate 198) to the package leads 102 of the package 100 of FIG. 6 or to the balls 126 of the package 122 of FIG. 8.
A wafer passivation stack 202 (typically a stack of dielectric material layers comprising, e.g., silicon dioxide, silicon nitride, silicon carbide or combinations thereof) is deposited over the bond pads 200 and selectively etched to form openings that expose regions of the copper bond pads 200. Aluminum pads or caps 212 are deposited within the openings.
A final passivation layer 214 (typically a multi-layer stack with the constituent layers not shown in FIG. 10) comprising, for example, silicon carbide, silicon nitride, silicon dioxide or combinations thereof, is deposited and selectively etched to form openings that expose the underlying aluminum pad 212. An under-bump metallurgical (UBM) layer (or layers) is deposited and selectively etched to form UBM structures 218 that overlay and contact the aluminum pad 212 and overlay a region of the final passivation layer 214. A solder bump 220 is formed over the UBM structures 218 to form the flip-chip interconnect.
With the final passivation layer 214 disposed over the aluminum cap 212, certain structure position management matters must be considered when locating and forming the opening in the layer 214 for receiving the UBM structures 218 and the solder bump 220. Typically this opening (having a largest dimension of about 70-80 microns) is smaller than the aluminum pad 212 (having a largest dimension of more than about 100 microns) and thus must be properly located relative to the pad 212. The UBM structure 218 is typically smaller than the aluminum pad 212. These variations in size must be properly managed and positional tolerances established to ensure that the solder bump 220 is ultimately conductively connected to the copper pad 200.
As illustrated in FIG. 10, it is also desired for the final passivation layer 214 to extend over edges 212A of the aluminum pad 212. For example, the opening in the passivation layer 214 is typically smaller by several microns (about four microns in one example) than the aluminum pad 212 to permit the passivation layer material to cover and protect the edges 212A and protect the aluminum pad 212 from environmental effects such as oxidation. As the overlap region is increased by shrinking the passivation layer opening, the protection provided by the passivation layer 214 improves (and the resistance to electromigration may be degraded.
Since the solder bumps 220 require a larger bonding area than the bond wires 114 of FIG. 1, the aluminum pads 212 employed in flip chip interconnects should be larger than the conventional bond pads 110 of FIG. 1, requiring that the openings in the final passivation layer 214 also be made larger. When scaling up these dimensions, the relationship between the aluminum pads 212 and the final passivation layer openings must be maintained to protect the aluminum pads 212. The present invention teaches methods and structures to provide such protection.